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Understanding IST Technology

Introduction to IST Technology
IST History
IST Methodology
IST Overview

Introduction to IST Technology

The following information is designed to give the first time reader a basic understanding of Interconnect Stress Testing (I.S.T.) Technology. The enclosed overview discusses the history, methodology, and general overview of IST testing. We understand that you will require more specific information regarding the principles of IST technology, performance base-lining, specifications and correlation data, this information can be made available when we understand which approach would be best suited for your applications.

It appears that our technology is able to perform a much-needed accelerated reliability/performance assessment function for the printed wiring board (PWB), assembly and end use industries that is presently unavailable with traditional accelerated stress testing and/or micro section analysis. We offer highly accelerated stress testing within a similar time frame and cost, relative to traditional micro sectioning.

We are presently receiving strong interest from all segments of the electronics industry. With Asia-based PWB manufacturing customers now purchasing systems; we have over 90 IST systems in the field.  Approximately 30% of our systems owners are located in the United States, Canada, United Kingdom and Germany. The majority of our North American and European customers utilize our IST test services, thus avoiding capital expense. The most common interests are related to product and process characterization, troubleshooting, correlation studies and prescreening prior to traditional accelerated (thermal oven) testing.

Our mission is to establish IST as the industry standard test method for the assessment of PWB interconnect reliability.  In 2000 we established IST as an IPC compliant test method (TM-650 - Method 2.6.26), for the assessment of plated through holes (PTH) and inner layer to PTH barrel inter-connections. Over the past 12 years we have been continually involved with various IPC task groups and committees, to establish correlations with traditional test methods and developing additional applications to compliment the IST methodology.

As additional systems are installed into our customer sites, our test services continue to expand, and our customers openly disseminate their performance data to the industry through technical papers, we anticipate an increased level of awareness and understanding of our technology. The sharing of performance data within organizations like the IPC and consortium based studies, will drive the industry toward standards and specification that will establish IST as the primary tool for accelerated stress testing, creating data for determining the criteria for future product acceptance and rejection.

Following a review of the enclosed information, we recommend the next phase is to contact us to discuss how our technology could be best used for your application.  Our general approach is to work in conjunction with the PWB supplier(s), this enables all participants to establish performance baselines, that are used for future reference, e.g. when quantifying the impact of assembly and rework (especially lead free), changes to designs, base materials, new chemistries, etc.

Our initial objective is to understand your critical product attributes, and then duplicate these features into an IST test coupon design.  This is followed by the release of a complete design package to enable coupon construction. When we receive the coupons IST testing is completed, the test results are documented into a test report, including failure analysis and comparisons to historical product performance baselines.

Included in this document is information that describes a historical overview of the past 20 years of IST technology development and deployment, with a basic overview of our methodology.  Please review the attached information and contact us with your questions or comments. We trust that this initial IST information is sufficient to give you a general understanding of our technology and coupon designs. We hope we have identified a potential application that will establish a future working relationship.

Please call or email us if you need references from existing customers of IST systems or users of our test services, or if you have any specific questions on the methodology or coupon designs, we look forward to hearing from you.

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IST History

Interconnect Stress Testing (IST) technology was original developed from the electrical stress testing concept called "power cycling" developed by Mr. Rama Munikoti (et. al.) at Northern Telecom (Nortel) in the mid 80’s. The present IST developers (who also worked at Nortel at that time) had the responsibility of manufacturing the various type of test vehicles, with known good and bad levels of quality, specifically in the drilling and plated through hole (PTH) processes. The different quality conditions were used to support the determination of the viability for the original power cycling concept.

The initial results showed great promise and a white paper was written to discuss the results. In 1989, having left Nortel and joined Digital Equipment Corporation of Canada (DEC), we established a joint R&D program between the two companies. Our intentions were to duplicate the same capability at DEC, to establish the repeatability and reproducibility of the power cycling methodology. The results identified lower than expected/acceptable correlation. Nortel elected to discontinue further R&D activity and DEC "decided to go it alone" to better understand how to achieve excellent repeatability and correlation with industry standard test methods (Microsectioning and Air to Air thermal cycle testing).

During the early 90's, DEC developed new testing principles and established improved temperature controlling algorithms, these fundamental changes also afforded the technology a new name (IST). The majority of R&D was focused toward new coupon designs concepts, and totally automation the IST system. Our internal motivations were to develop a faster, cheaper, more repeatable and reproducible accelerated stress test method to quantify the integrity of our VAX 9000 back-planes, produced at one of our internal PWB facilities.  The VAX9000 was DEC’s entry into the super computer market, the board measured 48" x 36", 24 layers, .250" thick, with blind and buried vias, with a nickel/gold finish over the total board surface. We were mounting 16 MCM's, which required 64 separable interconnect flex on the surface of each back-plane. IST was developed as the tool to characterize the manufacturing process and quantify the integrity of the total PTH interconnects.

We started working with the IPC in 1992, and was involved with various round robin test plans to determine the correlation of our test method to thermal ovens and liquid to liquid testing (basically a repeat of the IPC-TR-579). In addition to IST, other new technologies including 2 similar electrical stress test methods and an accelerated fluidized sand bath method were compared. In the interim IST was being made available to the PWB industry through a testing service business unit. Customers would submit products to the DEC failure analysis labs. IST was completed, in conjunction with Mil-Std Thermal cycling. Excellent correlation was achieved and identical failure modes and mechanisms were found between the different methods.

In 1994, new IST principles were developed to establish the capability to detect inner-layer to PTH barrel (post) interconnect separations. Working with the PWB industry and various chemical suppliers, we were able to re-create numerous types and levels of post separations within the interconnects.  IST was able to consistently detect the separations and achieved a .98%+ correlation coefficient with microsection analysis.
The IST system electrically stresses and monitors both the PTH and post interconnects simultaneously, but independently, creating 2 "dimensions" of failure.  The system clearly identifies whether the PTH or the post interconnect were degrading as individual failure mechanisms, or whether there were interactions between the different failure modes.

We also received extensive interest for this capability, related to evaluating the integrity of direct metalization, when compared to traditional electroless coppers. We completed an IPC/EPA study that compared the performance of 25 different metallizations using both IST testing and microsection analysis (completed by Robisan Labs). The results showed excellent correlation between the two methods.

The requirement for our testing service has concentrated on the performance of plated PTH interconnect and the detection of foil cracking, or post separations, specifically at the PWB manufacturing base. An increased number of PWB manufacturers and end use customers are experiencing various degrees of interconnect quality issues like post separations in their products.  The defects ranged from fine line separations to “gross” separations, the gross levels were being found during the assembly electrical test operations, where they are measured as intermittent opens. We were involved with many companies throughout the industry that were working to troubleshoot the problem at the vendor base; we supplied immediate feedback that determined the manufacturer’s ability to turn the problem on and off.

The PWB manufacturers were frustrated with the traditional microsection analysis method because of the randomness and inconsistency of their test results. IST supplied timely information that not only determined the presence of interconnect quality issues, but also determines the severity of the problem.

In 1996, IPC released a new test method. The methodology was designed to replace/support traditional accelerated stress testing and microsection analysis. The methodology was released in the IPC TM-650 manual with test method number 2.6.26.

Other activities included working with the Aerospace, Avionics, and Automotive industries to correlate with their 1000-hour (-65C - +125C) thermal cycling test. Multiple studies were completed on chemical and material DOE's.

IST technology was established as the preferred method for quantifying the integrity of microvias (our test vehicles measured 3" x 0.5" and contained 2,000+ microvias).

There was strong demand from companies that were required to meet extensive long term reliability testing, they were using our service as a prescreening tool, to determine their ability of their products to pass their extended test requirements. Our testing took 1 day to give assurances of passing their 1000-hour (41 days) test.

Using IST as an electrical test delivered the capability to remove the human factor from the decision making process of product acceptance or rejection. The test rapidly quantified whether any "flaw" within the interconnect has a detrimental impact on the total interconnect integrity.  We were starting to understand the "hierarchy of failure" the test method was demonstrating which were dominant and which were latent failure mechanisms.

In 1996 PWB Interconnect Solutions Inc. was incorporated and received the exclusive licensing rights for IST Technology, from DEC. Our company portfolio includes selling IST systems, IST test services, failure analysis capability and consulting to the electronics industry.  The technology was initially deployed to multiple PWB manufacturers, chemical suppliers and end users across North America and Europe.  The earliest sales were delivered Viasystems (3 systems), Merix Corporation (1 system), Electrochemicals (1 system) and Hewlett Packard – Germany (1 system). We focused our attention toward mid and large size independent PWB manufacturers, Chemical and Material suppliers, and the larger computer-manufacturing corporations that were dependent on their external PWB supply base.

With these the early installations we were able to start to grow the business, this was complimented by our IST test services. We had customers from all segments of the industry. The service activities usually follow a similar pattern, working through some or all of the following activities:

1. Discussions related to process characterization, material/chemistry evaluations, process monitoring, vendor assessment/qualification, impact of assembly/rework, trouble-shooting, correlation studies, reliability studies, etc.
2. Test vehicle design, this is a critical stage, to ensure that we include or re-create the actual product or failure mode conditions, that are needed to be quantified.
3. Selection of design, if not was already available a test vehicle would be created.
4. Release of test vehicle design file to customer.
5. Work with PWB vendor(s) to ensure coupons are produced correctly, to deliver the maximum return of information.
6. Construction of test vehicles.
7. Receiving coupons at IST test lab, for accelerated stress testing and failure analysis, generation of test report with failure analysis and references to baseline data, conclusions/ recommendations.

The service side of the business has become an excellent, cost and time effective introduction to IST technology, the customer has the opportunity to use the technology without capital investment. Once the customer has utilized the services, they have an ability to determine the ROI, and justify the potential future purchase of an IST system.

Our IST system customer base was primarily in North America and European, although this has now shifted toward the testing service business. With the shift of manufacturing offshore the majority of system installations now taking place in the Far East, over the past 5 years 80% of system sales are made in main land China, Taiwan, Korea and Japan. We have established offices in each of these countries to deliver customer support and sales and marketing capability.

We have expanded our service business; to include a US based (Huntsville AL) location that offers a complete IST testing service, including full failure analysis capability. This facility permits us to work directly with the US military.

We continue to encourage the entire IST user community to compile and report on their product reliability/performance data. This information will be used to establish future standards and specification related to acceptance/rejection criteria, with regard to the performance of the total interconnect.  Electronic interconnects are continually changing, specifically in the areas of density and levels and types of structures within the same product. This requires that we work closely with all segments of the industry to ensure our designs are consistent to the latest technology and are able to find the evolving failure modes that are quite different from the traditional barrel cracks and interconnect separations.

With the advent of lead free compliance and the associated increased stresses that PWB have to experience and “survive”, we have had to develop new capabilities to understand the total impact on product reliability.  The conditions created by lead free assembly and rework cycles can be as destructive to the base materials as much the interconnect structures, this made it necessary to invent techniques that permit us to measure the materials ability to survive assembly without the potential for delamination.  This philosophy is now included on all IST coupon designs, our strategy is to determine if the materials were damaged before submitting the coupons into IST testing.  This effort is complimented by our investment in state of the art materials analysis equipment; which has helped us to understand how certain material properties can contribute to overall product performance.

Today both PWB Inc. and the acceptance of IST Technology as the industry standard test method continues to grow, despite the fact that the circuit board industry has experienced major (severe) changes throughout the past 5 years. This is a testament to the technology and the workforce behind the scenes, who are dedicated to delivering the best possible product, whether it is equipment, designs, services, analysis and/or customer support.

We appreciate your interest in our technology and company; please do not hesitate to contact us for further information.

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IST Methodology

The principles behind I.S.T. are quite interesting and surprisingly simple. The I.S.T. system automatically passes a predetermined constant DC current through a specifically designed PWB interconnect test vehicle (coupon), the current elevates the temperature of the metals and adjacent materials. The temperature to which the coupon is heated is directly proportional to the measured resistance and the amount of current that is passed through the conductors, pads and holes.  There is a physical principle, that can be described mathematically, that defines the relationship of the current being passed and the resistance (temperature) of the interconnect. This is further influenced by the resistivity of the metalization (a value that describes how hard it is for electrons to flow through the entire conductive structure).

The IST system uses this principle to raise the resistance/temperature of the circuits to a predetermined value, usually 150°C for reliability testing or 230°C to 260°C for simulated assembly. Once the specified resistance/temperature has been achieved, the system turns off this current and cooling begins. After the 3 minute heating stage the coupons are forced air cooled for approximately 2 minutes, enabling the coupon to return to ambient, this constitutes a single thermal cycle. The specified resistance/temperature level for reliability testing is designed to be just below the glass transition temperature of the base material (150C).

During each thermal excursion, the system continuously monitors the minute resistance changes in the PTH, blind, buried, micro-via or inner layer to barrel (post) interconnects. As the temperature of the interconnect increases (or decreases), the resistance values of the interconnect (i.e. traces, pads and hole barrels) should also measure proportional changes. The IST system is designed to quantify the ability of the interconnect structures to withstand these thermal/mechanical stress’ and strains. Testing is usually completed on the as manufactured and the assembled state, determining when the products reaches the point of interconnect degradation or failure.

With high quality interconnects, the integrity of the various via types, inner layer connections or micro-via to capture pad interconnects are unaffected for several hundreds of these cycles, the difference between the resistance values before, during and after are virtually zero.

If changes in resistance are measured between progressive cycles, whether they are positive or negative, then something has potentially changed within the structure of the interconnect. The IST systems measurement is very sensitive to minute changes in resistance. In other words, if a failure mode initiates, the measured difference in resistance is usually very small (sub-milliohm). Subsequently, the ability of the interconnect to withstand further stressing is reduced, which leads to larger progressive measured increases in resistance.  When larger resistance changes are detected, a defect that ultimately leads to a product failure, has initiated/started, this stage is referred to as failure propagation or damage accumulation. If the changes reach a level of 10% increase in resistance, a structural failure has occurred within the interconnect. IST is designed to monitor these changes and stop the stressing at a pre-determined (low) level of failure. 

This permits early intervention in order that failure analysis can be initiated at an early stage of failure propagation, or before the damage accumulation destroys the critical information relating to failure initiation.

Using this methodology allows the IST system to determine when a defect begins to develop as well as how rapidly the damage accumulates. The changes are monitored on 3 independent circuits; the first is the usually the heating circuit which carries the current through the internal layers, and can monitor the resistance changes associated to inner layer to plated through hole barrel, measuring for interconnect separations or foil cracking. The second and third circuits receive no current, these circuits are responsible for measuring the PTH, blind, buried or micro-via interconnect reliability. The system compares each circuits to determine whether via cracking or post separation are the more dominant failure mechanism.

The system automatically repeats this temperature cycle over and over, measuring the resistance continuously until a rejection criteria is achieved; rejection could be set at a predetermined increase in resistance or a pre-set number of cycles. All test conditions/parameters are automated; the operator presets them before IST testing is started.

The data collection, reporting and analysis portion of the software are also automated. The data that is obtained by this system is more that just pass/fail; it records every part of every cycle on all circuits under test. The IST system not only graphically displays the performance of each coupons performance throughout the test, but it also provides feedback as to when a defect has initiated, and will lead to an interconnect failure.

This is important because it allows the operator to select a lower level of resistance change in order that the failure mechanism can be detected at the point of failure inception, as opposed to waiting for a catastrophic failure. This is a capability that no other integrity test method on the market has today. In most methods utilized today, it is only possible to investigate defects after they have progressed to a failure (open circuit) state. The very process of a catastrophic failure destroys most of the evidence that determines the potential root cause.

IST utilizes the internal interconnect to heat the coupon; heat generation is created throughout the daisy chain of copper conductors, pads and vias. Throughout testing, any local areas of increased resistance within the interconnect will cause localized heating to occur. Measurements above a 1% increase in elevated resistance signify failure inception/initiation. The increased resistance is caused by areas of localized strain (thinner plating/voids/poor plating distribution, inner layer (post) separations Etc.). 

The point of failure initiation and the rate of defect acceleration are pieces of information critical to the diagnosis of the root cause of the problem.

If the test coupons are to be used to compare the performance of both plated through barrel and inner layer to barrel reliability, the IST system ideally requires a minimum of 6 layers (4 internal/2 external). Double sided and 4 layer designs are generally used for plated through hole reliability testing only. Coupons are designed to ensure thermal uniformity across the entire test circuit area. The relationship between the resistance for conductors, pads and holes must be controlled to allow uniform heating within the substrate. Electrical modeling is performed to achieve the correct balance.

Our website contains a number of generic IST coupon designs to cover most of the conventional interconnect technologies. The designs come with a complete gerber package, including instructions that enable the CAD/CAM operator to create a coupon that duplicate the actual product. The designs are very flexible, the coupons can contain any number of layers, copper weights, constructions, hole/pad and anti-pad diameters, etc.

Additionally, a library of 500+ coupon designs exist at PWB, they encompass a wide variety of technologies presently being tested, they include:

• Layer counts: 2 to 40+ layers
• Interconnects: PTH, micro-via to capture pad, inner layer to barrel (post)
• Via types: Through hole, Blind, Buried, and Micro-via (stacked or staggered)
• Pads in/Pads out for lands on internal layers
• Signal, power/ground or mixed planes
• Grid sizes: .016”, .020”, .024”, .028”, .032", .040”, .050", .060” .080", or .100"
• Hole/Pad sizes: As required
• Copper weights 1/4oz to 10oz
• DOE comparisons: PTH Vs Blind, PTH Vs Micro-via, stacked Vs Staggered, Etc.
• Individual coupons or test panels with multiple coupons are available.
• Coupon size: Generally 5" x 1/2" (smaller/larger as preferred)
• Capacitance measurement to confirm product construction and material types
• Planarization circuits to confirm copper thickness on each layer.
• Counter-boring/Back-drilling test circuits to confirm correct drill depth
• Test vias to determine drill to inner layer registration

We generally interface with the PWB manufacturer when the design files are released to ensure they understand the requirement for coupon construction. Coupons are produced and sent to the IST testing facilities for testing, failure analysis is completed, technical reports are written that describe the products performance relative to baseline data for similar technologies. We are involved with all segments of the industry, testing the full range of technology levels. We are usually asked to support product/process performance studies, material/chemical comparison studies, correlation studies with existing test methods, and product/process troubleshooting.

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The following Information is designed to provide an overview of various elements of our company and technology More detailed information is available in the Documentation section.

PWB Interconnect Solutions

Businesses - IST systems / Test services Consulting

System installations in North America, Europe, Asia

Negotiating additional systems - Worldwide

Systems supporting test services

Introduced new IST system software in Visual Basic, and developed future capability to test solder joint reliability

Established support centers within Asia & Europe

Established independent test service contractor in U.S. 

I.S.T. System Development - Chronology (16 years)

IST Principles developed


Beta systems deployed


Patents received


Interconnect testing introduced


IST exclusively licensed to PWB Interconnect Inc.


IST Systems delivered to customers       


IPC test methodology (2.6.26)


Expanded in U.S., Europe & Asia              


Alternative Test Methods - Competitive Analysis


Thermal Cycling

Liq / Liq

Fluid Sand

Solder Float

Test Type/Temp

Stress (65/+125C)

Shock (35+125C)

Shock (25-260C)

Shock (25-260C)






Time to Result Hr





Cost of Test (/100cyc.)





Cost of Ownership (5 yrs)





Data Collection

Additional @$10K

Additional @$10K

Additional @$10K



Hard wired Drainage, Compressed Air

Hard wired Drainage, Compressed Air

Hard wired Drainage, Compressed Air

Requires Exhaust




Emits Lead

Emits Lead

Competitive Analysis



Thermal Cycling


Test Type/Temp

Stress (25-150C)

Stress (65/+125C

Shock (-35/+125C)





Failure Detection

Early detection

Not applicable

Not applicable

Cost of Ownership




Cost of Test (/500cyc)




Data Collection


Additional @10K

Additional @10K


PTH + Post




260 C

145 C

160 C

Time to Results (hrs)





Portable AC Outlet

Hard wired Drainage, Compressed Air

Hard wired Drainage, Compressed Air









Activities with the I.P.C. and I.S.T. Partners

Completed repeatability and reproducibility studies with multiple IST users and traditional test labs

Determine the applicability of the I.S.T. approach to effectively quantify the presence and influence of post separation on PTH interconnect reliability

Establish impact of various assembly conditions on long term reliability of total interconnect

Completed Correlation to thermal oven testing

Developing Test Protocol & Specifications for the detection of material delamination

Review ongoing performance/development efforts at IPC committee meetings

Support various IPC Lead Free Programs  (HDPUG & Halogen Free)