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C99-51 Evaluation of IST (D.B. Barker and M.D. Blattau, Kevin Cluff (Honeywell))

The objective is to develop a finite element model to understand interconnect stress testing results and to relate them to oven chamber testing and field usage

PWB Dielectric Substrates for Lead-Free Electronics Manufacturing (Douglas Leys and Steven P. Schaefer)

This paper presents a comparison of four (4) different commercially available PWB substrate materials, including one produced specifically to handle lead-free soldering, using both traditional thermal shock testing and accelerated thermal cycling. The use of the Interconnect Stress Test (IST) was chosen for the accelerated life cycle test.

PWB Reliability Evaluation Methods (Wennei Chen, Bill Bjorndahl, Brian Parrish, Bill Birch, and Ronald Carter)

This evaluation examined IST and IPC coupons associated with several PWB designs and PWB fabrication lots… This study found a correlation between IST and thermal shock test severity. The results indicated that a total of 300 IST cycles would induce fatigue effects on plated barrels at least as severe as 100 thermal shock cycles.

Advanced Testing Using Real Life Evaluation and Statistical Data Analysis (Jason Furlong and Michael Freda)

Increasing complexity and shrinking lead time are reducing the time available for system level qualification and reliability testing. These increased time-pressures to qualify materials, processes, PWB vendors and/or products are requiring the electronics industry to modify their testing methodologies and apply alternative statistical analysis techniques.

Application of Reliability/Survival Statistics (Jason Furlong and Michael Freda)

Historical results from IST testing on Sun Microsystems’ Enterprise Server Products will be discussed, followed by data analysis results from the latest round of IST testing at Sun in support of our coming generation of lead-free servers.

Via Life vs. Temperature Stress Analysis of Interconnect Stress Test (Michael Freda)

As published in CircuiTree, March 2005. Also provides insight into IST use at Sun Microsystems

IST Correlation Study Between Multek Asia, PWB Interconnect Solutions, and Multek Germany (Bill Slough)

Objective: To conduct an interlaboratory Interconnect Stress Test comparison between PWB Interconnect Solutions Inc. (PWB), Multek Germany (BBN) and Multek Asia (ASIA).

Interconnect Reliability of HDI Printed Wiring Boards (Tatsuo Suzuki - Nec Toppan Circuit Solutions, Inc)

Presented in the ECWC 10 Conference, IPC Printed Circuits Expo; includes article and slides.

Lead-Free Product Transition: Impact on PCB Design and Material Selection (Gary Brist and Gary Long)

Electronic products are being stressed by increasing operating temperatures and higher assembly temperatures. Silicon and product power consumption are increasing as the silicon densities and signaling frequencies increase. And, the transition to lead-free solders is resulting in higher thermal excursions during assembly. Both of these conditions are impacting material selection during product design and are having an impact on product qualification, and influencing long-term via reliability.

Effects of Lead-Free Soldering on “Plating” Vias (Jack Fellman - Rohm and Haas Electronic Materials)

This paper will describe the effects of assembly at higher temperatures on materials and processes to produce the plated through vias and microvias. Factors that effect reliability of through vias and microvias will be discussed along with ways reliability can be assessed. Electroless copper plating is challenged to provide adhesion to the new laminate materials. Electroplated copper must keep up with the new design requirements, higher aspect rations, etc. “Difficulty Factor” is a concept used to express the effects of board thickness and via diameter on the plating process. Surface finishes, such as ENIG and Lead-free HASL, can have a positive effect on reliability because they participate in the formation of the solder joint.

Microvia Reliability: Concerns in the Lead-Free Assembly Environment (Paul Andrews, Gareth Parry, Paul Reid)

Traditional microvias have been considered to be the most reliable interconnect structure within a printed wiring board. With the advent of lead-free assembly, the vulnerability of high density interconnects to fail has increased. This is due to the elevated temperatures experienced during assembly and rework. Over the last 24 months, microvias have been found to fail during assembly and in their end-use environment. This was noticed in North America and Europe in the spring of 2003. This paper outlines a case study of microvia failure; reliability test methods, failure analysis, fabrication process considerations, and impact of tin/lead and lead-free assembly process on microvia reliability.

U.S. EPA-IPC Design for the Environment PWB Project (Deborah Boger, Bill Birch, and Susan Mansilla)

The purpose of this study was to evaluate the performance of technologies that making PWB through-hole conductive. Many of these technologies are known as “direct metallization” (DM) processes. In order to complete this evaluation, PWB panels, designed to represent industry ‘middle-of-the-road’ technology, were manufactured at one facility, run through individual ‘making holes conductive’ (MHC) lines at 26 facilities, then electroplated at one facility.

Copy of IPC-TM-650 Test Methods Manual - DC Current Induced Thermal Cycling Test

This is a link to the IPC Test Method TM 650 2.6.26. The Test Method outlines the step by step process to test the coupons from sample preparation to plotting the results from the stress cycling measurements.